View MAX9485_831984.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3315; Rev 0; 7/04
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
Programmable Audio Clock Generator
Features
27MHz Crystal with 30ppm Frequency Reference Two Buffered Output Ports with Multiple Audio Clocks: 256, 384, or 768 Times fS Supports Standard and Double Sampling Rates (12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz, and 96kHz) I2C Interface or Hardwired Output Clock Selection Separate Output Clock Enable Low Jitter Typical 21ps (RMS at 73.728MHz) No External Components for PLL Integrated VCXO with 200ppm Tuning Range Small Footprint, Thin QFN Package, 4mm x 4mm
General Description
The MAX9485 programmable multiple-output clock generator provides a cost-efficient solution for MPEG-2 audio systems such as DVD players, DVD drives for multimedia PCs, digital HDTV systems, home entertainment centers, and set-top boxes. The MAX9485 accepts an input reference frequency of 27MHz from a crystal or system reference clock. The device provides two buffered clock outputs of 256, 384, or 768 times the chosen sampling frequency (fS) selected through an I 2 CTM interface or hardwired inputs. Sampling frequencies of 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, or 96kHz are available. The MAX9485 also offers a buffered 27MHz output and an integrated voltage-controlled oscillator (VCXO) that is tuned by a DC voltage generated from the MPEG processor. The use of VCXO allows the audio system clock to lock with the overall system clock. The MAX9485 features the lowest jitter in its class, guaranteeing excellent dynamic performance with audio ADCs and DACs in an MPEG-2 audio system. The device operates with a 3.3V supply and is specified over the -40C to +85C extended temperature range. The MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP and 4mm x 4mm 20-pin thin QFN packages.
MAX9485
Ordering Information
PART MAX9485ETP MAX9485EUP TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 20 Thin QFN-EP* 20 TSSOP
*EP = Exposed pad. I 2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Applications
Digital TVs Set-Top Boxes Home Entertainment Centers DVD Players HDTVs
Pin Configurations
GND_P VDD_P SAO2 MCLK SAO1
TOP VIEW
VDD_P 1 GND_P 2 TUN 3 X1 4 X2 5 VDD 6 SCL/FS0 7 SDA/FS1 8 FS2 9 GND 10 20 SAO2 19 SAO1 18 MCLK 17 VDD TUN X1 X2 VDD SCL/FS0
19
1 2 3 4 5 10 7 6 8 9
20
18
17
16 15 14
VDD CLK_OUT2 GND CLK_OUT1 MODE
MAX9485
16 CLK_OUT2 15 GND 14 CLK_OUT1 13 MODE
MAX9485
EXPOSED PAD (GROUND)
13 12 11
GND
12 RST FS2 SDA/FS1 11 GND
TSSOP
THIN QFN
________________________________________________________________ Maxim Integrated Products
GND
RST
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Programmable Audio Clock Generator MAX9485
ABSOLUTE MAXIMUM RATINGS
VDD, VDD_P to GND ...............................................-0.3V to +4.0V GND_P to GND ...................................................................0.3V All Inputs and Outputs to GND...................-0.3V to (VDD + 0.3V) Short-Circuit Duration of Outputs to GND ..................Continuous Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 11mW/C above +70C) ......... 879mW 20-Lead Thin QFN (derate 16.9mW/C above +70C).............................................................1349mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF)...........> 2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = VDD_P = 3.0V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, VDD = VDD_P = 3.3V.) (Note 1)
PARAMETER High Level-Input Voltage Low Level-Input Voltage Input Current High Level-Input Voltage Low Level-Input Voltage Input Open Level Input Current Output High Level Output Low Level Input High Level Input Low Level Input Current Low-Level Output Input Capacitance POWER SUPPLY (VDD, VDD_P) Power-Supply Ranges Power-Supply Current VDD, VDD_P IDD+IDD_P CLK_OUT1, CLK_OUT2 at 73.728MHz, no load, VTUN = 3.0V 3.0 3.3 12 3.6 V mA SYMBOL VIH1 VIL1 IIL1 VIH2 VIL2 VIO2 IIN VOH1 VOL1 VIH3 VIL3 IIN VOL3 CIN Input voltage = 0 or VDD IOL3 = 4mA 8.4 Input open Input voltage = 0 or VDD IOH1 = -4mA IOL1 = 4mA 0.7 x VDD 0 -1 Input voltage = 0 or VDD CONDITIONS MIN 2.0 0.0 -20 2.5 0.0 1.3 -10 VDD - 0.6 0.4 VDD 0.3 x VDD +1 0.4 TYP MAX VDD 0.8 +20 VDD 0.8 2.0 +10 UNITS V V A V V V A V V V V A V pF
LVCMOS/LVTTL INPUTS (MODE, RST, X1) (Note 2)
THREE-LEVEL INPUTS (FS0, FS1, FS2, SAO1, SAO2)
LVCMOS/LVTTL OUTPUTS (CLK_OUT1, CLK_OUT2, MCLK)
I2C INTERFACE INPUT AND OUTPUT (SCL, SDA)
2
_______________________________________________________________________________________
Programmable Audio Clock Generator
AC ELECTRICAL CHARACTERISTICS
(VDD = VDD_P = 3.0V to 3.6V, TA = -40C to +85C, output frequency is 73.728MHz, CL = 20pF, unless otherwise noted. Typical values are at TA = +25C, VDD = VDD_P = 3.3V.) (Note 3)
PARAMETER VCXO (MCLK) Crystal Frequency Crystal Accuracy Tuning Voltage Range VCXO Tuning Range TUN Input Impedance Output Clock Frequency Output Clock Accuracy Output Duty Cycle Output Jitter Output Rise Time Output Fall Time Tuning Response Time Power-On Settling Time tMJ tMR tMF tTUN TPO1 RMS Figure 8 Figure 8 Figure 9 Figure 9 256 x fS Frequency Range (Note 5) Clock Rise Time Clock Fall Time Duty Cycle Output Clock Period Jitter Frequency Settling Time Power-On Time tRJ tFST TPO2 RMS Figure 1 Figure 9 CLK_OUT1, 2 at 73.728MHz (Note 6) CLK_OUT1, 2 at 36.864MHz fout tR1 tF1 384 x fS 768 x fS Figure 8 Figure 8 45 8.192 12.288 24.576 2 2 50 21 37 10 15 ms ms 55 RTUN fMCLK VTUN = 1.75V VTUN = 1.75V (Note 4) 45 VTUN VTUN = 0 to 3.0V 0 -200 94 27 50 55 28 2 2 10 5 24.576 36.864 73.728 ns ns % ps MHz 65 fXTL Nominal frequency 27 30 3.0V +200 MHz ppm V ppm k MHz ppm % ps ns ns s ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9485
CLOCK OUTPUTS (CLK_OUT1, CLK_OUT2)
_______________________________________________________________________________________
3
Programmable Audio Clock Generator MAX9485
I2C TIMING CHARACTERISTICS
(VDD = VDD_P = 3.0V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, VDD = VDD_P = 3.3V; Figure 7.) (Note 1)
PARAMETER Serial Clock Bus Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of SDA and SCL, Receiving Fall Time of SDA and SCL, Receiving Fall Time of SDA, Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD, STA tSU, STA tSU, STO tHD,DAT tSU,DAT tLOW tHIGH tR tF tF tSP Cb (Notes 3, 8) (Notes 3, 8) (Notes 8, 9) (Notes 3, 10) (Note 7) 1.3 0.6 0.6 0.6 0.05 100 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0 300 300 250 50 400 0.9 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns s s ns ns ns ns pF
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design and characterization. When X1 is used as an external reference. Guaranteed by design and characterization; limits are set at 6 sigma. Includes crystal accuracy. FXTL = 27MHz. Nominal frequency. See frequency selection paragraph in the Applications Information section. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 8: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. Note 9: Bus sink current is less than 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. Note 10: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
Programmable Audio Clock Generator
Typical Operating Characteristics
(VDD = VDD_P = 3.3V, TA = +25C.)
MAX9485
SUPPLY CURRENT vs. LOAD CAPACITANCE
MAX9485 toc01
SUPPLY CURRENT vs. VTUN
MAX9485 toc02
SUPPLY CURRENT vs. OUTPUT FREQUENCY
VTUN = 1.5V CL = 20pF 40 SUPPLY CURRENT (mA)
MAX9485 toc03
50 VTUN = 1.5V fCLK_OUT = 73.728MHz 40 SUPPLY CURRENT (mA)
50 CL = 20pF fCLK_OUT = 73.728MHz 40 SUPPLY CURRENT (mA)
50
30
30
30
20
20
20
10
10
10
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF)
0 0 0.5 1.0 1.5 VTUN (V) 2.0 2.5 3.0
0 0 10 20 30 40 50 60 70 80 OUTPUT FREQUENCY (MHz)
OUTPUT CLOCK RISE/FALL TIME vs. LOAD CAPACITANCE
MAX9485 toc04
MCLK PULLING RANGE vs. VTUN
CX1 = CX2 = 4.7pF 200 PULLING RANGE (ppm) 100 0 -100 -200 -300 CX1 = CX2 = 6.8pF CX1 = CX2 = 5.6pF
MAX9485 toc05
3.0 2.5 RISE/FALL TIME (ns) 2.0 1.5 1.0 0.5 0 0 4 8 12 16 RISE TIME (tR) FALL TIME (tF) VTUN = 1.5V fCLK_OUT = 73.728MHz
300
20
0
0.5
1.0
1.5 VTUN (V)
2.0
2.5
3.0
LOAD CAPACITANCE (pF)
MCLK PERIOD JITTER vs. OUTPUT FREQUENCY
MAX9485 toc06
CLK_OUT PERIOD JITTER vs. OUTPUT FREQUENCY
VTUN = 1.5V CL = 15pF 400 PERIOD JITTER (psRMS)
MAX9485 toc07
50 VTUN = 1.5V CL = 15pF 40 PERIOD JITTER (psRMS)
500
30
300
20
200
10
100
0 0 10 20 30 40 50 60 70 80 OUTPUT FREQUENCY (MHz)
0 0 10 20 30 40 50 60 70 80 OUTPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
Programmable Audio Clock Generator MAX9485
Pin Description
PIN TSSOP 1 2 3 4 5 6, 17 7 TQFN 19 20 1 2 3 4, 15 5 NAME VDD_P GND_P TUN X1 X2 VDD SCL/FS0 FUNCTION PLL Power Supply. Bypass VDD_P with a 0.1F and 0.001F capacitor to GND_P. PLL Ground VCXO Tuning Voltage Input. Apply 0 to 3V at TUN to adjust the VCXO frequency. Connect TUN to VDD when driving X1 directly with a 27MHz input reference clock. Crystal Connection 1. Connect a fundamental mode crystal between X1 and X2 for use as a VCXO, or drive X1 directly with a 27MHz input reference clock. Crystal Connection 2. Connect a fundamental mode crystal between X1 and X2 for use as a VCXO, or leave X2 unconnected when driving X1 with a 27MHz system reference clock. Digital Power Supply. Bypass VDD with a 0.1F and 0.001F capacitor to GND. Serial Clock/Function Selection Input 0. When MODE = low, SCL/FS0 functions as the I2C serial clock input. When MODE = high, SCL/FS0 functions as a three-level input to select sampling frequency. Serial Data I/O/Function Selection Input 1. When MODE = low, SDA/FS1 functions as the I2C serial data input/output. When MODE = high, SDA/FS1 functions as a three-level input to select output frequency scaling factor. Function Selection Input 2. When MODE = high, FS2 functions as a three-level input to select sampling rate. When MODE = low, voltage levels at FS2 do not affect device operation. Ground Reset Input. Drive RST low resets the I2C register to its default state. RST is internally pulled to VDD. Mode Control Input. When MODE = low, the I2C interface is active. When MODE = high, the hardwired interface is active, and function selection is programmed by SCL/FS0, SDA/FS1, and FS2. Mode is internally pulled to GND. Output Clock Port 1. CLK_OUT1 operates at 256/384/768fs, depending on the function selection. CLK_OUT1 is pulled low when disabled. Output Clock Port 2. CLK_OUT2 operates at 256/384/768fs, depending on the function selection. CLK_OUT2 is pulled low when disabled. Master System Clock Buffered Output. MCLK outputs the 27MHz clock generated by the internal VCXO. MCLK is pulled low when disabled. I2C Device Address Selection Input 1 or MCLK Output Enable Control Input. When MODE = low, SAO1 is a three-level I2C device address programming input. When MODE = high, SAO1 controls MCLK enable/disable. I2C Device Address Selection Input 2 or CLK_OUT Output Enable Control Input. When MODE = low, SAO2 is a three-level I2C device address programming input. When MODE = high, SAO2 controls CLK_OUT1 and CLK_OUT2 enable/disable. Exposed Pad. Connect EP to ground.
8
6
SDA/FS1
9 10, 11, 15 12
7 8, 9, 13 10
FS2 GND RST
13
11
MODE
14 16 18
12 14 16
CLK_OUT1 CLK_OUT2 MCLK
19
17
SAO1
20
18 Exposed Pad
SAO2
--
EP
6
_______________________________________________________________________________________
Programmable Audio Clock Generator
Functional Diagram
VDD VDD_P
MAX9485
MAX9485
MCLK
COUNTER N
COUNTER M
PHASE DETECTOR AND LOOP FILTER
CLK_OUT1 VCO PLL DIVIDING COUNTER CLK_OUT2
TUN X1 VCXO X2 MODE CONTROL REGISTERS SCL/FS0 SDA/FS1 FS2
RST
RESET
GND
SAO1 SAO2
GND_P
Detailed Description
The MAX9485 uses an input reference frequency of 27MHz from a crystal or system reference clock. The device provides two buffered clock outputs of 256, 384, or 768 times the chosen sampling frequency (fS) selected through an I 2 C interface or hardwired inputs. Sampling frequencies of 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, or 96kHz are available. The MAX9485 offers a buffered 27MHz output and an integrated VCXO tuned by a DC voltage generated from the MPEG system. The device operates with a 3.3V supply.
Reference and Output Clock
The MAX9485 uses the 27MHz crystal or reference clock (master clock) from the audio system and generates an output of 256, 384, or 768 times the audio system sampling frequency (fS). Connect a fundamental
mode crystal between X1 and X2 or drive X1 with a 27MHz system clock. The choices of sampling frequencies are 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, and 96kHz. The MAX9485 offers two identical outputs: CLK_OUT1 and CLK_OUT2. In the following, the CLK_OUT is used to refer to both outputs. Table 1 shows the relations of fS and the output frequency. Select the output frequency by programming the I2C register or hardwiring inputs FS0, FS1, and FS2. CLK_OUT settling is typically 15ms from power-on or from applying the clock to X1. Delay time from sampling frequency change to CLK_OUT settling is 10ms (typ). Figure 1 illustrates CLK_OUT transient timing in the I2C programmed case. The I2C register is set through a master-write data transfer. The frequency settling time tFST is counted from the end of the next ACK pulse of the written byte in SDA until the CLK_OUT is settled.
_______________________________________________________________________________________
7
Programmable Audio Clock Generator MAX9485
Table 1. Sampling Frequency and Output Clock
SAMPLING FREQUENCY fS (kHz) 12 32 44.1 48 64 88.2 96 256 x fS (MHz) 3.072 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 CLK_OUT 384 x fS (MHz) 4.608 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 768 x fS (MHz) 9.126 24.5760 33.8688 36.8640 49.1520 67.7376 73.7280 Standard Standard Standard Standard Double Double Double SAMPLING RATE
HIGH SDA LOW
ACK PULSE tFST
Voltage-Controlled Crystal Oscillator (VCXO)
The MAX9485 internal VCXO produces a 27MHz reference clock for the PLL used to generate CLK_OUT1 and CLK_OUT2. The oscillator uses a 27MHz crystal as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a range of 200ppm. The tuning voltage VTUN can vary from 0 to 3V as shown in Figure 2. Use an AT-cut crystal that oscillates at 27MHz on its fundamental mode with 30ppm. Use a crystal shunt capacitor less than 12pF, including board parasitic capacitance. Choose an oscillator with a load capacitance less than 14pF to achieve 200ppm pullability. VCXO, a free-run oscillator, and the buffered output MCLK are not affected by power-on reset and external reset. VCXO has a 5ms settling time at power-on and 10s at a change of the VTUN voltage. The MAX9485 can be used as a synthesizer with a 27MHz input reference clock. For this mode, connect the 27MHz input clock to X1. Connect TUN to VDD and leave X2 open. This configuration is for applications where the micro tuning is not needed and there is a 27MHz system master clock available.
CLK_OUT
STABLE
TRANSITION
STABLE
Figure 1. CLK_OUT Transient Timing
27.0054
VCXO OUTPUT FREQUENCY (MHz)
27
400ppm
Chip Reset Function
The MAX9485 has an internal reset function. The device resets at power-up or can be externally reset by driving RST low. The reset function sets the registers to default values. MODE sets the device's programming mode at power-up. When MODE = low, the device is set to software-programmable mode. Set MODE = high for hardwired mode. If MODE = low, the reset sets default values for CLK_OUT1 and CLK_OUT2 to 256 x f S with f S = 32kHz. If MODE = high, the reset sets CLK_OUT1 and CLK_OUT2, according to the values of the hardwired inputs.
26.9946 0V 3V VTUN
Figure 2. VCXO Tuning Range
8
_______________________________________________________________________________________
Programmable Audio Clock Generator
The internal power-on reset completes after 1024 cycles of the reference clock starting when V DD is greater than 2.2V with a tolerance of 0.4V. When using the internal power-on reset, RST must be high. Figure 3 shows power-on reset timing. The internal reset function also accepts an external forced reset by driving RST = low. The reset is triggered when RST = low and completes after 1024 reference clock cycles. When a reset is initiated, any pulses on RST during the 1024 reference clock cycles are ignored. If RST is held low at the end of a reset cycle, reset does not initiate until a high-to-low transition is detected at RST. Figure 4 shows external reset timing.
Software and Hardwire Control Modes
The MAX9485 sampling frequency, sampling rate, and clock outputs can be programmed through the I 2C 2-wire interface (software mode, MODE = low), or hardwired directly through three-level inputs (hardwire mode, MODE = high). The offered functions for each mode are shown in Table 2. CLK_OUT and MCLK are pulled low when disabled.
MAX9485
Hardwire Mode Programming (MODE = High)
In hardwire mode, FS2 selects the sampling rate (Table 3). With FS2 = low, the sampling rate is standard. With FS2 = high, the sampling rate is doubled. When FS2 = open, the 12kHz standard rate is selected, overriding the setting of FS0. FS1 selects the scaling factors: 256, 384, and 768 (Table 4). FS0 selects the sample frequencies: 32kHz, 44.1kHz, and 48kHz (Table 5). When MODE = high, inputs SAO1 and SAO2 enable or disable the clock outputs (Tables 6 and 7). CLK_OUT and MCLK are pulled low when disabled.
VDD 2.6V 2.2V 1.8V
Table 2. Selectable Functions
POWER-ON RESET RANGE
FUNCTIONS
INTERNAL RESET RESET PERIOD = 1024 CYCLES AT 27MHz RESET REMOVAL
HARDWIRE MODE MODE = HIGH
SOFTWARE MODE MODE = LOW
Standard sampling frequencies: 12kHz, 32kHz, 44.1kHz, 48kHz Double sampling frequencies: 64kHz, 88.2kHz, 96kHz CLK_OUT1, CLK_OUT2, MCLK: enable/disable
Figure 3. Power-On Reset Timing
RST
(MIN: 20ns)
Table 3. Sampling Rate Selection
FS2 Low High SAMPLING RATE Standard (32kHz, 44.1kHz, 48kHz) Doubled (64kHz, 88.2kHz, 96kHz) Standard (12kHz)
INTERNAL RESET
RESET PERIOD = 1024 CYCLES AT 27MHz
RESET REMOVAL
Open
Table 4. Frequency Scaling Factors
FS1 Low OUTPUT SCALING FACTOR 256 384 768
Figure 4. External Reset Timing
High Open
_______________________________________________________________________________________
9
Programmable Audio Clock Generator MAX9485
Table 5. Selection of Sampling Frequency
FS0 Low High Open SAMPLING FREQUENCY (kHz) 32 44.1 48
Table 8. Register Address Selection
SAO1 Open Low High Open Low High Open Low High SAO2 Open Open Open Low Low Low High High High I C DEVICE ADDRESS 110 0000 110 0011 110 0010 110 0100 110 1000 111 0000 111 0001 111 0010 111 0100
2
Table 6. MCLK Enable/Disable Control
SAO1 Low High Open MCLK Disabled Enabled Reserved
Table 7. CLK_OUT Enable/Disable Control
SAO1 High/low High/low High/low SAO2 Open Low High CLK_OUT1 Enabled Enabled Disabled CLK_OUT2 Enabled Disabled Enabled
Table 9. Control Register Bit Mapping
BIT C7 C6, C5 C4 C3, C2 C1, C0 FUNCTION MCLK enable/disable CLK_OUT2, CLK_OUT1 enable/disable Sampling-rate selection Frequency-scaling factors Sampling-frequency selection
Software Mode Programming (MODE = Low)
In software mode, the I2C interface writes or reads an 8-bit control register in the MAX9485. The control register controls the rate settings and the clock outputs. Since there is only one register in the MAX9485, no address is assigned to this register. The device has a programmable 7-bit address for the I2C bus, selected by SAO1 and SAO2 (Table 8). At power-up with MODE = low, the MAX9485 reads the state of SAO1 and SAO2, then latches the I2C device address. Table 9 shows the control register bit mapping. Bit C7 enables the MCLK output. Bits C5 and C6 enable the clock outputs CLK_OUT1 and CLK_OUT2, respectively. Bit C4 selects the sampling rates. Bits C3 and C2 choose the output frequency-scaling factor. Bits C1 and C0 determine the sampling frequency. The details are shown in Tables 10-14.
Table 10. MCLK Enable/Disable Control
C7 0 1 MCLK Disabled Enabled
Table 11. CLK_OUT1, 2 Enable/Disable Control
C6 1 1 0 0 C5 1 0 1 0 CLK_OUT2 Enabled Enabled Disabled Disabled CLK_OUT1 Enabled Disabled Enabled Disabled
Serial Interface
The MAX9485 control interface uses a 2-wire I2C serial interface. The device operates as a slave that sends and receives data through clock line SCL and data line SDA to achieve bidirectional communication with the master. A master (typically a microcontroller) initiates all data transfers to and from the MAX9485, and generates the SCL clock that synchronizes the data transfer. The
Table 12. Sampling Rate Selection
C4 0 1 SAMPLING RATE Standard Doubled
10
______________________________________________________________________________________
Programmable Audio Clock Generator
Table 13. Frequency Scaling Factors
C3 0 0 1 1 C2 0 1 0 1 OUTPUT SCALING FACTOR 256 384 768 Reserved
SCL S START CONDITION P STOP CONDITION SDA
MAX9485
Table 14. Sampling Frequency Selection
C1 0 0 1 1 C0 0 1 0 1 SAMPLING FREQUENCY (kHz) 12 32 44.1 48
S
Figure 5. Start and Stop Conditions
MASTER-WRITE DATA STRUCTURE SLAVE ADDRESS 7 BITS R/W A DATA 8 BITS A P
Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selection. However, when set, it selects 12kHz sampling frequency.
SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. The SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain SCL output.
MASTER-READ DATA STRUCTURE S SLAVE ADDRESS 7 BITS R/W A DATA 8 BITS A P
Start and Stop Conditions
Both SCL and SDA remain high when the interface is idle. The active master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. After communication, the MAX9485 issues a STOP (P) condition by transitioning SDA from low to high while SCL is high, freeing the bus for another transmission (Figure 5). If a START or STOP occurs while a bus transaction is in progress, then it terminates the transaction.
A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE S = START CONDITION P = STOP CONDITION MASTER TRANSFERS TO SLAVE SLAVE TRANSFERS TO MASTER
Figure 6. Serial Interface Data Structure
Data Transfer and Acknowledge
Following the START condition, each SCL clock pulse transfers 1 bit. For the MAX9485 interface, between a START and a STOP, 18 bits are transferred on the 2-wire bus. The first 7 bits are for the device address. Bit 8 indicates the writing (low) or reading (high) operation (R/W). Bit 9 is the ACK for the address and operation type. Bits 10 though 17 form the data byte. Bit 18 is the ACK for the data byte. The master always transfers
the first 8 bits (address + R/W). The slave (MAX9485) can receive the data byte from the bus or transfer it to the bus from the internal register. The ACK bits are transmitted by the address or data recipient. A low ACK bit indicates a successful transfer (Acknowledge), a high ACK bit indicates an unsuccessful transfer (Not Acknowledge). Figure 6 shows the structure of the data transfer. During a write operation, if more synchronous data is transferred, it overwrites the data in the register. During a read operation, if more clocks are reset on SCL, the SDA continues to respond to the register data.
______________________________________________________________________________________
11
Programmable Audio Clock Generator MAX9485
SDA tSU, DAT tLOW SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 7. 2-Wire Serial Interface
(tR1, tMR) 80% CLK_OUT, MCLK 20%
(tF1, tMF) 80% 2.2V 20%
VDD
t
RISE AND FALL TIME MEASURED BETWEEN 20% AND 80%. SDA CLK_OUT1 OR CLK_OUT2
STOP PULSE AFTER WRITING STOP EDGE
Figure 8. CLK_OUT, MCLK Rise and Fall Time
Applications Information
Crystal Selection
When using the MAX9485's internal VCXO with an external crystal, connect the crystal to X1 and X2. Choose an AT-cut crystal that oscillates at 27MHz on its fundamental mode with 30ppm. Use a crystal shunt capacitance less than 12pF, including board parasitic capacitance. Choose an oscillator with a load capacitance less than 14pF to achieve 200ppm pullability. Note: Pulling range may vary depending on the crystal used. Refer to the MAX9485 Evaluation Kit for details.
tPO2
tFST
VTUN
MCLK tPO1 tTUN
Figure 9. VCXO and PLL Settling Time
12
______________________________________________________________________________________
Programmable Audio Clock Generator
Output CLK Frequency Setting with Low Jitter
A specific frequency could be achieved through multiple settings (Table 1) such as different sampling rate and multiplication factors (256, 384, and 768). However, due to the difference of internal structure, the CLK outputs jitter may be different for each setting. Table 15 lists CLK output frequencies and jitter for the various settings. For best performance, the user should choose the setting that gives the lowest jitter at a specific frequency.
Table 15. Jitter Measurements of Output CLKs
FOUT (MHz) 73.728 67.7376 49.152 36.864 36.864 33.8688 33.8688 24.5760 24.5760 24.5760 22.5792 18.4320 16.9344 16.3840 12.2880 12.2880 11.2896 9.126 8.1920 4.608 3.072 SCALING FACTOR 768 768 768 768 384 768 384 768 384 256 256 384 384 256 256 384 256 768 256 384 256 fS (kHz) 96 88.2 64 48 96 44.1 88.2 32 64 96 88.2 48 44.1 64 48 32 44.1 12 32 12 12 TRJ(RMS) (ps) 21 23.2 42.6 40 37 44 41.3 66 92 50 55.1 59 69 134 84.8 170 100 106 250 198 324
MAX9485
Power-Supply Bypassing and Ground Management
The MAX9485's high oscillator frequency makes proper layout important to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock output. Return GND to the highest-quality ground available. Bypass VDD and VDD_P with 0.1F and 0.001F capacitors, placed as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs.
______________________________________________________________________________________
13
Programmable Audio Clock Generator MAX9485
Typical Application Circuit
I2C INTERFACE TO SET AUDIO CLK RATE
FILTERED PWM CONTROL VOLTAGE FOR VCXO
TUN CLK_OUT1
AUDIO CLK: 256/384/768fS
DUAL-CHANNEL AUDIO DAC
FRONT AUDIO SIGNALS
MAX9485
27MHz CRYSTAL AUDIO CLK GENERATOR CLK_OUT2 DUAL-CHANNEL AUDIO DAC SURROUND AUDIO SIGNALS
MCLK 27MHz
AUDIO ENCODED DATA FROM DVD/HDD/BS-TUNER
MPEG DECODER
L CH AUDIO DATA R CH AUDIO DATA
DUAL-CHANNEL AUDIO DAC
BACK AUDIO SIGNALS
Chip Information
TRANSISTOR COUNT: 9817 PROCESS: CMOS
14
______________________________________________________________________________________
Programmable Audio Clock Generator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9485
______________________________________________________________________________________
15
Programmable Audio Clock Generator MAX9485
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1
2
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9485

	To Download MAX9485 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .